| 摘要 |
A digital signal processing circuit, which is embodied by a digital signal processor (i.e., DSP), comprises at least an address counter and a coefficient RAM which is provided to store coefficients used for convolution processing to be performed. An overall storage area of the coefficient RAM exists between a first address and a last address. An external device provides control information including an initial count number and up/down information. The address counter counts a number of pulses included in a timing signal, which is produced in synchronism with bit clocks in a sampling period, so as to output a count number as a write address for the coefficient RAM. The address counter performs either an up-counting or a down-counting in accordance with the up/down information; and the count number thereof is increased or decreased from the initial count number. Hence, the coefficients sequentially inputted are written into the coefficient RAM at the respective write addresses. When the write address is increased to the last address or is decreased to the first address, the address counter outputs a carry signal, by which the coefficients inputted afterwards are not written into the coefficient RAM but are automatically transferred to the next DSP in which they are stored.
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