| 摘要 |
A high speed bus structure for a multi-port bridge for controlling the flow of data packets through the multi-port bridge by using a limited number of bus commands. The bridge includes a memory for storing packets and a plurality of ports. Each port includes a receive buffer, a transmit buffer and a memory pointer buffer. A data packet is received by the receive buffer of a port. As the packet is still being received, a look-up table is utilized to determine which is the appropriate destination port for the packet. The destination ports are notified of their status as destination ports by raising a signal line of the communication bus corresponding to each destination port, referred to as a "bit-map". If the memory pointer buffer in the destination port is nearly full, the destination port generates a jam request. The source port receives the jam request and, in response, discards the incoming packet and sends a jam signal. If the destination port is available to receive the packet directly from the source port, the destination port receives the packet simultaneously as the packet is stored in the memory device. Once the packet is stored, a memory pointer is placed on the communication bus. The memory pointer is stored in the destination port until the packet can be retrieved from the memory for transmission by the destination port.
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