| 摘要 |
An integrated circuit chip is fabricated as several circuit modules that are synchronized with a clock signal, by the following steps. Initially, a hardware description language is used to describe a functional behavior for a first module on the chip which generates an intermodule signal, and describe a functional behavior for a second module on the chip which processes the intermodule signal. Thereafter, a slow circuit embodiment of the first module is synthesized with port timing constraints which permit the intermodule signal to be generated in twice the cycle time TCY of the clock signal, and a slow circuit embodiment of the second module is synthesized with port timing constraints which permit the intermodule signal to be processed in twice the cycle time of the clock. Then, a timing analysis program is run on the slow circuit embodiment of the first and second modules to thereby obtain a first delay DELTA 1 in which the intermodule signal is actually generated, and obtain a second delay DELTA 2 in which the intermodule signal is actually processed. Subsequently, a fast circuit embodiment of the first module is synthesized which generates the intermodule signal within a delay of (TCY)( DELTA 1) DIVIDED ( DELTA 1+ DELTA 2) and a fast circuit embodiment of the second module is synthesized which processes the intermodule signal within a delay of (TCY)( DELTA 2) DIVIDED ( DELTA 1+ DELTA 2).
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