| 摘要 |
PROBLEM TO BE SOLVED: To advance a pipeline processing by reducing delay due to a branch- destination instruction read by requesting a memory to read the branch- destination instruction of a branch instruction to an instruction buffer when the branch instruction is decoded. SOLUTION: At an IF stage, instructions set in BIRP 400 and BIRS 500 are decoded by a 1st instruction decoder 900. When a branch instruction is decoded by the 1st instruction decoder 900, an instruction read request for a branch-desntination instruction is issued to an instruction cache 100. The instructions set in the BIRP 400 and BIRS 500 are stored in IFR 100, and the instruction set in the BIRP 400 is transferred to a selecting circuit 1010. Thus, two instructions are decoded in every machine cycle at the IF stage as a 1st instruction decoding stage and transferred to a D stage as a 2nd instruction decoding stage. At the 2nd instruction decoding stage, the instructions set in IRP 1200 and IRS 1300 are decoded by a 2nd instruction decoder 1700.
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