发明名称 Method and architecture for complex datapath decimation and channel filtering
摘要 A decimation and channel filter (100 or 23) in an oversampled system includes a combined decimation and channel filtering architecture for simultaneously processing in-phase and quadrature phase complex input signals. A decimation filter (24) of the combined decimation and channel filter provides sampled outputs to a memory (108) to provide an intermediate result (604), which is stored in the memory (108) in a first format (608). A channel filter (26) of the combined decimation and channel filter processes (610) a decimation final result of the decimation filter in a second format in the memory to provide a final result. This architecture minimizes cost and current drain in a complex signal path decimation and channel filtering process. In addition, a channel filtering algorithm is used to ideally minimize current drain by a factor of 2.
申请公布号 US6470365(B1) 申请公布日期 2002.10.22
申请号 US19990378932 申请日期 1999.08.23
申请人 MOTOROLA, INC. 发明人 RAHMAN MAHIBUR;THOMAS CHRISTOPHER T.
分类号 H03H17/04;H03H17/06;(IPC1-7):G06F17/10 主分类号 H03H17/04
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