发明名称 METHOD OF VERIFYING MULTI-POWER-SOURCE INTEGRATED CIRCUIT AND VERIFYING APPARATUS THEREFOR
摘要 PROBLEM TO BE SOLVED: To provide a verifying method of a multi-power-source integrated circuit which efficiently detect a voltage connection violation in circuit without any omission before a layout is designed. SOLUTION: Provided is a voltage connection violation verifying apparatus 103 which prepares connection information (net list information 101) on circuit components constituting the integrated circuit and further names of terminals of the circuit components and operating source voltage information on the terminals as characteristic information (cell library information 102) on the circuit components and detects a connection violation regarding an operating voltage only by referring to operating source voltage information on the terminals of mutually connected cells according to those pieces 101 and 102 of information without defining connection rules of the cells. In this constitution, a connection other than the equal-potential source voltage of the integrated circuit to be verified can efficiently be detected as a voltage connection violation without any omission. COPYRIGHT: (C)2004,JPO
申请公布号 JP2003345853(A) 申请公布日期 2003.12.05
申请号 JP20020151652 申请日期 2002.05.27
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 UMEDA TAKASHI
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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