发明名称 PROCESSOR AND INSTRUCTION CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To issue an asymmetric instruction to a particular destination without deepening a control logic in a decoding cycle. SOLUTION: When a plurality of instructions are all symmetric instructions, a symmetric instruction issuing part 56 issues the symmetric instructions to a plurality of reservation stations 22-1 and 22-2 provided in each of different computing units 26 and 28 until they are full. In an asymmetric instruction issuing part 56, when it is discriminated that there is an asymmetric instruction in the plurality of instructions and the rest are symmetric instructions, the asymmetric instruction is unwound in a multiple flow of a precedent flow and a subsequent flow and it is issued to the reservation station 22-1 provided in correspondence to the particular computing unit 26, and the remaining symmetric instructions are issued to the plurality of reservation stations 22-1 and 22-2 provided in each of the different computing units 26 and 28 until they are full at an issuing cycle that is different from that of the asymmetric instruction. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004038751(A) 申请公布日期 2004.02.05
申请号 JP20020197305 申请日期 2002.07.05
申请人 FUJITSU LTD 发明人 YOSHIDA TOSHIO
分类号 G06F9/30;G06F9/38;(IPC1-7):G06F9/38 主分类号 G06F9/30
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