SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit which has enhanced ESD resistance in order to perform various settings of the power supply terminal. SOLUTION: In the semiconductor integrated circuit, an output terminal PO is electrically connected to an output buffer 1, a protection PMOS transistor MP2 is inserted between a node N3 connected to the output terminal PO and a grounding terminal P22, and a gate of the protection MOS transistor MP2 is connected to the power supply terminal P12. The power supply terminals P11, P12 are formed in the insulated condition with each other within a chip and the power supply voltages VDD1, VDD2 are supplied independently to such power supply terminals P11, P12. A capacitance value CVDD1 of a parasitic capacitance C1 between the power supply terminal P11 and a ground terminal P21 and a capacitance value CVDD2 of a parasitic capacitance C2 between the power supply terminal P12 and the ground terminal P22 are set to satisfy the relationship of CVDD1 <