发明名称 MEMORY
摘要 PROBLEM TO BE SOLVED: To provide a memory in which a disturb phenomenon that erases data in non-selective memory cells is suppressed. SOLUTION: The memory is provided with bit lines BL0 to BL7, word lines WL0 to WL7 which are arranged to cross the bit lines BL0 to BL7 and a memory cell array 1 which is connected between the bit lines BL0 to BL7 and the word lines WL0 to WL7 and includes memory cells that hold data "1" or data "0". In addition to batch reading operations conducted for selected memory cells, a voltage Vp, which is an inverse polarity voltage with respect to the voltages (-Vp1 and -Vp0) applied to the non-selective memory cells during a reading operation, is applied to at least the non-selective memory cells. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005203009(A) 申请公布日期 2005.07.28
申请号 JP20040006396 申请日期 2004.01.14
申请人 SANYO ELECTRIC CO LTD 发明人 SAKAI TADASHI
分类号 G11C11/22;G11C11/409;H01L27/105;(IPC1-7):G11C11/22 主分类号 G11C11/22
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