Clock recovering apparatus and method

摘要

A circuit for generating a clock based on time of receipt of a RZ (return to zero) data bit stream using a known clocking frequency. An internal actuated counter is used to generate a lower frequency data clock and is reset to an initial condition whenever the incoming data phase deviates mote than a prescribed amount from the phase of the generated clock. A non-zero data pattern is required to periodically resynchronize the derived clock with the incoming data.