| 摘要 |
PURPOSE:To generate the parity bit of a binary-decimal addition result at a high speed by composing the circuit of a partial adder which sums up an addend and augend, bit by bit, a carry look ahead circuit, and a parity-bit and parity correction item generating circuit. CONSTITUTION:Augends a0 to a15 and addends b0 to b15 are inputted, four bits by four bits, to partial adders 1 to 4 for one digit and group generating item CG and group proper gate item GP from adders 1 to 4 are inputted to carry look-ahead circuit 5. On the basis of augend bit ai and addend bit bi, bit generating item Gi and bit proper gate item are obtained and the both and parity bits Pa0, Pa1, Pb0, and Pb1 equivalent to 8-bit units of augends and addends are inputted to parity generating circuit 6 for binary addition results and parity correction item circuit 7 correcting a parity bit error at the time of decimal addition, thereby obtaining S0 to S15 of binary addition results of addition results, parity bits PS0 and PS1, and parity correction items P10 to P13. |
