发明名称 DIGITAL COUNTER CIRCUIT
摘要 PURPOSE:To secure the correspondence of the display width of the minimum unit to one unit of the pulse and then to have the counting action and the decision in the phase direction by giving the time delay to the count input pulse supplied to the counter and then setting the phase difference in terms of time. CONSTITUTION:Both sin-wave 2a and cos-wave 2b featuring the 90 deg. phase difference are supplied from encoder 2 to 4-fold pulse circuit 4 which decides the shift direction after the waveform shaping at Schmitt circuit 3. The pulse receives the 4-multiplication at circuit 4, the delay circuit plus the multiplexer each to secure the minimum measurement unit for each pulse interval. The output of circuit 4 receives the polarity inversion at polarity inversion circuit 5 and via the signal of zero detection part 9 of up-down counter 10, and the polarity inversed signal centering on the basic point zero is sent to driver 13 to secure the display of the polarity at polarity display part 14. At the same time, counter 10 is controlled based on the count zero. The pulses of the forward and backward phases sent from circuit 5 are compounded 6 and then supplied to counter 10 after delayed by a fixed time through delay circuit 7. And the output of counter 10 is displayed at display part 12 via decoder 11.
申请公布号 JPS5563136(A) 申请公布日期 1980.05.13
申请号 JP19780136507 申请日期 1978.11.06
申请人 ASAHI SEIMITSU KK 发明人 UDAGAWA GIICHI;KATOU MASAAKI
分类号 B43L13/00;G01D5/244;G01D5/245;H03K23/00;(IPC1-7):03K23/00 主分类号 B43L13/00
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