| 摘要 |
PCT No. PCT/JP79/00023 Sec. 371 Date Sep. 24, 1979 Sec. 102(e) Date Sep. 24, 1979 PCT Filed Jan. 30, 1979 PCT Pub. No. WO79/00564 PCT Pub. Date Aug. 23, 1979.A delay circuit is disclosed having (32, 34), a flip-flop circuit (36), and circuits (30, 40) for maintaining reset states during the presence of a first signal (Xo, Yo) and a gate circuit (38) inputted with a second signal (Sd) and controlled to open and close by the output from the flip-flop circuit, and capable of obtaining a relatively long time of delay from the end of the first signal to the interruption of the output of the second signal, with ease in a digital manner even if produced as an integrated circuit. The delay circuit is suitable for use with the channel selection circuit in electronic tuning radio receivers. |
