发明名称 MEMORY CIRCUIT
摘要 PURPOSE:To enable also to relieve manufacturing deficiency, by reading out two sets of memories in which the same data is written, and selecting the output data based on the detected output for coincidence, noncoincidence, and presence of error, etc. CONSTITUTION:Data S2A, S2B read out from memories 1A, 1B in which the same data is written, are compared at a coincidence circuit 2, and a detection signal SC being high or low level depending on agreement or disagreement is produced. Similarly, depending on the presence of error in the data S2A, S2B, high or low level detected output SEA or SEB is produced from an error detection circuit 3A or 3B, and fed to a selection circuit 4 provided with switch circuits 5A, 5B to which readout signals are fed. Further, the circuits 5A, 5B are controlled via an AND gate 8, exclusive OR circuit 7, selection section 9, AND gates 6A, 6B. Even if the signal SC is at low level due to a manufacturing deficient memory via an OR circuit 10, either one of the data S2A or S2B outputs to relieve the manufacturing deficient memory.
申请公布号 JPS56165991(A) 申请公布日期 1981.12.19
申请号 JP19800069109 申请日期 1980.05.24
申请人 NIPPON TELEGRAPH & TELEPHONE 发明人 UEOKA YASUSHIGE;TERAJIMA SATORU;ITOU HIROO
分类号 G06F11/08;G06F12/16;G11C29/00 主分类号 G06F11/08
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