发明名称 LEVEL CONVERTING CIRCUIT
摘要 PURPOSE:To decrease the number of elements, by connecting the first polarity transistor which has connected an output of the low voltage side and the reverse potential to the source and the gate, respectively, to the second polarity transistor, in a level converting circuit consisting of an IGFET. CONSTITUTION:In a level converting circuit consisting of an IGFET, reverse output potential V1 of the low voltage side by an inverter 21 is inputted directly to a P channel transistor TR24, also is inputted to a gate Vi of an N channel TR25 which has been by-passed to source potential VSS by a resister 23 through a capacity 22, and each drain of the trasistors 24, 25 is connected to each other and outputs voltage V0. Moreover, the reverse voltage V1 and the voltage V0 are connected to the source of a P channel TR26 and the gate, respectively, and its drain is connected to the gate of the transistor 25. Accordingly, since the TRs 24, 25 execute a push- pull operation to each other, the power consumption is reduced, and furthermore, when the reverse voltage V1 has become high voltage VDD as a direct current, the voltage V0 is set to the source potential VSS stably.
申请公布号 JPS5752225(A) 申请公布日期 1982.03.27
申请号 JP19800126521 申请日期 1980.09.11
申请人 SUWA SEIKOSHA KK 发明人 ASAKAWA TATSUJI
分类号 H03K19/0185;H03K5/02 主分类号 H03K19/0185
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