| 摘要 |
<p>A system for rapidly transferring data between a plurality of successive memory locations and a data output buss (10) includes a plurality of data latches (A0 A1, A2, A3) for storing data derived from successive memory locations.
<??>A corresponding plurality of.serially coupled decoders (D0, D1, D2, D3) are each associated with one of the data latches (A0 - A3). In response to an address input, one decoder (D0) is enabled for causing its associated data latch (A0) to output its stored data to the data buss (10). The one decoder (D0) then disables itself and enables the next decoder (D1) so that a second data latch (A1) outputs its stored data. The procedure is continued such that the data latches (A0 - A3) are caused to sequentially output their stored data.
<??>In addition, each of the decoders (D0 - D3) is associated with one of a plurality of input buffers (B0, B1, B2, B3) and the decoders (D0 - D3) are arranged to cause the input buffers (B0 - B3) to sequentially write input data into successive memory locations. </p> |
