| 摘要 |
PURPOSE:To output an accurate vertical synchronizing signal, by providing the 1st and 2nd counting means plus a shift register to sample the synchronizing signal every time a fixed time elapses, and as a result decreasing the adjusting areas of a detecting circuit as well as eliminating an error caused by the noise. CONSTITUTION:The 1st counting means 6 that supplies the video synchronizing signal V and the clock signal 8 starts counting of the signal 8 at the rise or fall of the signal V and detects the lapse of a certain time of >=0.5H and <=1H. At the same time, the 2nd counting means 10 starts counting of the signal 8 every time the means 6 detects the lapse of a certain time and delivers a pulse of a prescribed duration with each count of the signal 8. This pulse is applied to a shift register 13. The register 13 turns the signal 8 into a clock pulse to delay the horizontal driving signal HD given from the means 10 by a certain time. This delayed signal HD and the vertical synchronizing signal VD are applied to the 3rd FF14. The FF14 samples the signals VD every time the signal HD is supplied, and delivers the frame detecting signal 15 in an accurate way. |
