发明名称 |
SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WRITES TO AN ADDRESS |
摘要 |
A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored. |
申请公布号 |
EP3084608(A1) |
申请公布日期 |
2016.10.26 |
申请号 |
EP20140849874 |
申请日期 |
2014.10.03 |
申请人 |
INTEL CORPORATION |
发明人 |
LIU, YEN-CHENG;FAHIM, BAHAA;HALLNOR, ERIK G.;CHAMBERLAIN, JEFFREY D.;VAN DOREN, STEPHEN R.;JUAN, ANTONIO |
分类号 |
G06F11/30;G06F12/06 |
主分类号 |
G06F11/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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