| 摘要 |
PURPOSE:To increase a defect aiding rate of the title device and to make it suitable for frequent rewrites by making the whole memory cell array into an ECC (error checking and correcting) circuit constitution and making at least one part into a double cell constitution. CONSTITUTION:Address A0-Ai are supplied to a column decoder 2 to compose a memory cell array 1, address Aj-An are supplied to a row decoder 3, and a word line is selected by the decoder 3. The output voltage of the decoder 3 is level-converted by a high voltage level converting circuit 6, thereafter, it is impressed to the word line, and the decoder 2 is connected through a high voltage level converting circuit 7 to a Y selector 4 to select a bit line. On the other hand, to a control circuit 8 to control the action of the whole of the memory, enable signals the inverse of CE, the inverse of OE and the inverse of WE of a chip, an output, and a write, respectively, are supplied, and they are controlled by a timer 9 to which a clock generator 10 is connected. To the generator 10, a boosting circuit 11 is provided, and for a program to be obtained, a voltage Vpp is given to a sense amplifier/writing circuit 5. |
