| 摘要 |
<p>This provides clock signal synchronized with transmit data detect data accurately, to reduce the number of transmission line and to make the system simple. The propossed circuit is composed of parts, i.e. equalizer (10), noise reduction circuit (20), data detector (30), 'AND' gate (40), clock generator and counter block (50) and 'XOR' (exclusive OR) gate (60).</p> |
