| 摘要 |
<p>A semiconductor memory device is capable of holding stored contents of memory cells (MC) in a dynamic random access memory (DRAM) (101) effectively through a refresh operation. The memory device comprises a frequency-divider circuit (106), a refresh control circuit (105) for generating a word line activation signal (118) in response to an output of the frequency-divider circuit, and a control circuit (107) for controlling the frequency division value of the frequency-divider circuit. Even when switching directly after regular refreshing associated with read/write or other operation to self-refresh mode, as the first-time refreshing for all memory cells is performed at a higher restore level and at a shorter period than in regular refresh mode, the stored data of the memory cells can be refreshed at a low restore level. <IMAGE></p> |
