APPARATUS FOR CHANGING CHANNEL DATA SPEED AND DIVIDING CHANNEL DATA

摘要

The circuit includes a serial/parallel converting means (1) for controlling the incoming 400 Kbps serial data by means of a B channel clock (BCR) to output them in the form of a parallel data. A latching means (2) receives 8-bit parallel data from the serial/parallel converting means (1), and performs latching and reading on them in accordance with latch control signals and read control signals. A parallel/serial and speed converting means (3) converts the 8-bit parallel data of the latching means (2) to a serial data of 2048 Kbps in accordance with received signal load signals and 2048 Kbps bit clocks. An outputting means (4) outputs the data through 4 lines in the form of 2048 Kbps signals.