发明名称 |
APPARATUS AND METHOD FOR CYCLIC REDUNDANCY CHECK |
摘要 |
An apparatus and method for cyclic redundancy check device is provided. The apparatus includes a multiplicity of sub-block CRC parts configured to receive a bit sequence from each sub-block of a transport block that is divided into a multiplicity of sub-blocks and to perform CRC, and a Galois field adding part configured to add second codes, which are output from the multiplicity of sub-block CRC parts, in a Galois field, wherein each sub-block CRC part includes a Galois field multiplying part configured to generate a weight bit sequence by multiplying a first code, which is obtained from CRC calculation of a sub-block weight code that represents a weight allocated to each sub-block, and the bit sequence in the Galois field, and a linear feedback shift register including n-numbered registers and configured to output the second code by adding the weight bit sequence to each register in the Galois field. |
申请公布号 |
US2016371142(A1) |
申请公布日期 |
2016.12.22 |
申请号 |
US201615184723 |
申请日期 |
2016.06.16 |
申请人 |
CENTER FOR INTEGRATED SMART SENSORS FOUNDATION |
发明人 |
KIM Hye Ji;KIM Ji Hoon |
分类号 |
G06F11/10;G06F7/58;H04L29/08 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
1. An apparatus for cyclic redundancy check (CRC) operating with a polynomial having n degrees, the apparatus comprising:
a multiplicity of sub-block CRC parts configured to receive a bit sequence from each sub-block of a transport block that is divided into a multiplicity of sub-blocks and to perform CRC; and a Galois field adding part configured to add second codes, which are output from the multiplicity of sub-block CRC parts, in a Galois field, wherein each sub-block CRC part comprises: a Galois field multiplying part configured to generate a weight bit sequence by multiplying a first code, which is obtained from CRC calculation of a sub-block weight code that represents a weight allocated to each sub-block, and the bit sequence in the Galois field; and a linear feedback shift register including n-numbered registers and configured to output the second code by adding the weight bit sequence to each register in the Galois field. |
地址 |
Daejeon KR |