发明名称 不揮発性半導体記憶装置
摘要 A nonvolatile semiconductor memory device according to one embodiment comprises: a memory cell array comprising a plurality of NAND strings, each NAND string comprising a memory string comprising a plurality of memory cells and a dummy transistor; a plurality of word lines; a dummy word line; a plurality of bit lines; a source line; and a control circuit performing an erase sequence, the erase sequence repeating an erase operation to the memory cells and the dummy transistor and an erase verify operation of confirming whether the memory cells and the dummy transistor are changed to an erased state. The control circuit is configured to be able to perform, when the erase verify operation is unpassed, a dummy transistor erase operation of selectively changing the dummy transistor to an erased state and a dummy transistor erase verify operation of confirming whether the dummy transistor is changed to an erased state.
申请公布号 JP6042363(B2) 申请公布日期 2016.12.14
申请号 JP20140043990 申请日期 2014.03.06
申请人 株式会社東芝 发明人 平井 竜太;椎野 泰洋
分类号 G11C16/04;G11C16/02 主分类号 G11C16/04
代理机构 代理人
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