发明名称 Sequential circuit with error detection
摘要 Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
申请公布号 US9594625(B2) 申请公布日期 2017.03.14
申请号 US201514878985 申请日期 2015.10.08
申请人 Intel Corporation 发明人 Bowman Keith A.;Tschanz James W.;Kim Nam Sung;Lee Janice C.;Wilkerson Christopher B.;Lu Shih-Lien L.;Karnik Tanay;De Vivek K.
分类号 G06F11/07;G06F1/10;H03K3/037;G01R31/317 主分类号 G06F11/07
代理机构 Blakely, Sokoloff, Taylor & Zafman LLP 代理人 Blakely, Sokoloff, Taylor & Zafman LLP
主权项 1. A chip comprising: a datapath; a sequential unit comprising a data output and a data input coupled to the datapath; and a logic unit having a logic unit input connected to the data input of the sequential unit to detect a late data transition at the data input of the sequential unit, wherein when the logic unit fails to detect the late data transition the data still passes from the data input to the data output to prevent the datapath metastability.
地址 Santa Clara CA US