发明名称 |
Memory Migration Method and Device |
摘要 |
A memory migration method and device relate to the field of computer application technologies. A memory page is combined into a memory block, which reduces a quantity of migrations, and improves central processing unit (CPU) utilization. The method includes receiving, by a first node, a migration instruction sent by a second node, sequentially scanning each memory page between a physical address of a start memory page accessed by a target process and a physical address of an end memory page accessed by the target process, where the memory page is a memory page accessed by the target process or a memory page accessed by a non-target process, determining whether each memory page meets a block combination condition, combining a memory page that meets the block combination condition into a corresponding memory block, and migrating the corresponding memory block to a memory area of the second node. |
申请公布号 |
US2017068486(A1) |
申请公布日期 |
2017.03.09 |
申请号 |
US201615357240 |
申请日期 |
2016.11.21 |
申请人 |
Huawei Technologies Co., Ltd. |
发明人 |
Chu Lixing |
分类号 |
G06F3/06 |
主分类号 |
G06F3/06 |
代理机构 |
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代理人 |
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主权项 |
1. A memory migration method, comprising:
receiving, by a first node, a migration instruction sent by a second node, wherein the migration instruction is used to instruct to migrate, from a memory area of the first node to a memory area of the second node, all memory pages located on the first node and accessed by a target process, and wherein the target process is a process running on the second node; sequentially scanning, by the first node, each memory page between a physical address of a start memory page accessed by the target process and a physical address of an end memory page accessed by the target process; determining, by the first node, whether each memory page meets a block combination condition; combining a memory page that meets the block combination condition into a corresponding memory block; and migrating, by the first node, the corresponding memory block to the memory area of the second node. |
地址 |
Shenzhen CN |