METHODS OF FORMING CMOS BASED INTEGRATED CIRCUIT PRODUCTS USING DISPOSABLE SPACERS

摘要

Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.

主权项

1. A method of forming a CMOS integrated circuit product comprised of a first transistor of a first type and a second transistor of a second type formed on a substrate, wherein said second type is opposite to said first type, comprising:
forming a first gate structure for said first transistor and a second gate structure for said second transistor; forming a first spacer proximate both said first and second gate structures; forming an initial second spacer proximate said first spacer of said first transistor and a layer of second spacer material above said second transistor; forming first raised epi semiconductor material source/drain regions for said first transistor; performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of said first raised epi semiconductor material source/drain regions that is more hydrophilic that that of said semiconductor material of said first raised epi semiconductor material source/drain regions; and performing a first etching process on both said first and second transistors so as to completely remove said initial second spacer from said first transistor and said layer of second spacer material above said second transistor, while leaving said first spacer in position on both said first and second transistors.