ALLOCATION OF AN INTERCONNECT STRUCTURE COMPRISING SHARED BUSES TO SUPPORT THE EXECUTION OF INSTRUCTION SEQUENCES BY A PLURALITY OF ENGINES

摘要

A method for allocation of a shared interconnect structure in an integrated circuit is disclosed. The method comprises receiving a plurality of requests from a plurality of resource consumers of a plurality of engines to access a plurality of resources, wherein the resources are spread across the plurality of engines and contain data for supporting execution of multiple code sequences. The method also comprises contending for the plurality of resources in accordance with requests from the plurality of resource consumers. Finally, the method comprises accessing the plurality of resources via a global interconnect structure, wherein the global interconnect structure has a finite number of buses accessible each clock cycle, and wherein the global interconnect structure comprises a plurality of shared interconnect structures, wherein each shared interconnect structure is shared by each of a sender and each of a receiver.

主权项

1. A method for allocation of a shared interconnect structure in an integrated circuit, the method comprising:
receiving a plurality of requests from a plurality of resource consumers of a plurality of engines to access a plurality of resources, wherein the resources are spread across the plurality of engines and contain data for supporting execution of multiple code sequences; contending for the plurality of resources in accordance with requests from the plurality of resource consumers; and accessing the plurality of resources via a global interconnect structure, wherein the global interconnect structure has a finite number of buses accessible each clock cycle, and wherein the global interconnect structure comprises a plurality of shared interconnect structures, wherein each shared interconnect structure is shared by each of a sender and each of a receiver.