SEMICONDUCTOR DEVICE HAVING CAL LATENCY FUNCTION

摘要

One semiconductor device includes a command receiver receiving the command signal to generate a first internal command signal, and a latency control circuit activating a second internal chip select signal after elapse of first cycles of a clock signal since a first internal chip select signal is activated. The latency control circuit activates a second control signal when the chip select signal is maintained in an inactive state during second cycles of the clock signal that is larger than the first cycles. The command receiver is activated based on a first control signal. The first control signal is activated in response to the first internal chip select signal. The first control signal is deactivated in response to the second control signal.

主权项

1. A method for controlling a memory device comprising:
supplying a clock signal from a controller to the memory device; supplying a chip select signal from the controller to the memory device; supplying a mode register setting command from the controller to the memory device to set an internal mode signal in the memory device; supplying an access command from the controller to the memory device; wherein the controller activates the chip select signal at the same time as the access command if the mode register setting command sets the internal mode signal to a deactivated level and the controller activates the chip select signal a first predetermined number of cycles of the clock signal earlier than the access command if the mode register setting command sets the internal mode signal to an activated level; and wherein the memory device delays the chip select signal by the first predetermined number of cycles of the clock signal to provide a first internal chip select signal.