Bounded duty cycle correction circuit

摘要

A duty cycle correction circuit has a delay line comprising a plurality of current-starved inverters coupled together in series. An input of a first current-starved inverter receives an input clock signal. A relatively weak inverter is coupled in parallel with each of the current-starved inverters. A low pass filter having an operational amplifier has a differential input coupled to the output of the delay line for receiving an output clock signal. A single-ended output of the operational amplifier is coupled to current source and current sink transistors of each of the current-starved inverters to control the amount of delay provided by the delay line. The low pass filter corrects the duty cycle of the input clock signal so that the output clock signal has a 50 percent duty cycle. The relatively weak parallel-connected inverters insure that no clock pulses are skipped if the current-starved inverters fail to transition.

主权项

1. A duty cycle correction circuit comprising:
a plurality of series-coupled current-starved inverters having a beginning inverter for receiving a periodic input signal having a first duty cycle and a ending inverter for providing an output clock signal having a second duty cycle; a feedback circuit coupled between the last current-starved inverter and the beginning current-starved inverter of the plurality of series-coupled current starved inverters; and a plurality of inverters, an inverter of the plurality of inverters coupled in parallel with a current-starved inverter of the plurality of series-connected current-starved inverters.