发明名称 |
CMOS interpolator for a serializer/deserializer communication application |
摘要 |
The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for regulating a voltage for a high speed serializer/deserializer (SerDes) device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications. In various embodiments, phase-interpolator is implemented in conjunction with a delay-lock loop (DLL) and an SR latch, where one or more outputs of the DLL is used by the SR latch. Additionally, such techniques can be used for a variety of applications such as network and/or computer storage systems, computer servers, hand held computing devices, portable computing devices, computer systems, network appliances and/or switches, routers, and gateways, and the like. |
申请公布号 |
US9641313(B1) |
申请公布日期 |
2017.05.02 |
申请号 |
US201514826051 |
申请日期 |
2015.08.13 |
申请人 |
INPHI CORPORATION |
发明人 |
Gopalakrishnan Karthik S.;Ren Guojun;Mishra Parmanand |
分类号 |
H04L7/00;H04L7/033;H03L7/08;H03K5/14;H03K5/00 |
主分类号 |
H04L7/00 |
代理机构 |
Ogawa P.C. |
代理人 |
Ogawa Richard T.;Ogawa P.C. |
主权项 |
1. An integrated transceiver circuit device comprising:
a plurality of receivers coupled to a plurality of channels, each of the channels being configured for transmitting asynchronous data to one of the receivers, each of the receivers comprising:
a pre-amplifier device having an input and an output, the input being coupled to a channel associated with a receiver;a comparator device comprising an input coupled to the output of the pre-amplifier device, and configured to identify one or more binary states;a phase interpolator device coupled to the comparator device, the phase interpolator device being configured to perform a digital to phase conversion using information from the one or more binary states, the phase interpolator device comprising a phase interpolator core, a set-reset (SR) latch and a feedback loop, the SR latch comprising a set (S) input, a reset (R) input, and an output, the S input being configured to receive signals from the phase interpolator core, the feedback loop being coupled between the output of the SR latch and the R input, the feedback loop being characterized by a phase shift of about 180 degrees, the feedback loop including an operational transconductance amplifier (OTA) for generating a switching signal, the switching signal being associated with the R input; anda clock data recovery (CDR) circuit coupled to an output of the comparator device and configured to drive the phase interpolator device to synthesize a frequency and phase of a signal from the output of the comparator device; and a phase lock loop (PLL) device, the PLL device being common to and being coupled to each of the phase interpolator devices in the plurality of receivers. |
地址 |
Santa Clara CA US |