发明名称 Generation of delay values for a simulation model of circuit elements in a clock network
摘要 An approach for generating delay values for circuit elements in a clock network of a programmable IC includes determining for each clock resource in the clock network, different possible contexts of the clock resource. Each context specifies a combination of possible types of circuit elements in the context. Circuit elements of the possible types are selected from the different contexts, and configuration data is generated for implementation of respective ring oscillator circuits that include the selected circuit elements. The programmable IC is configured with the configuration data, and the programmable IC as configured with the respective ring oscillator circuits is operated. Respective delay values of the selected circuit elements are determined from output of the ring oscillator circuits. The delay values are stored in association with identifiers of the selected circuit elements in a memory arrangement.
申请公布号 US9639640(B1) 申请公布日期 2017.05.02
申请号 US201514693506 申请日期 2015.04.22
申请人 XILINX, INC. 发明人 Savithri Nagaraj;Ondris Robert M.;Hwang Chiao K.
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人 Maunu LeRoy D.
主权项 1. A method of generating delay values for circuit elements in a clock network of a programmable IC, comprising: determining from a specification of the programmable IC, respective locations of a plurality of clock test buffers and a plurality of test delay circuits on the programmable IC; determining with a computer processor for each clock resource in the clock network, different possible contexts of the clock resource, wherein each context specifies a combination of possible types of circuit elements of the programmable IC that are configurable for use with the clock resource; selecting circuit elements of the programmable IC of the possible types from the different contexts; generating configuration data for implementation of respective ring oscillator circuits that include the selected circuit elements on the programmable IC, wherein each ring oscillator circuit includes one of the selected circuit elements coupled between one of the plurality of clock test buffers and one of the plurality of test delay circuits; configuring the programmable IC with the configuration data that specifies the respective ring oscillator circuits including the selected circuit elements; operating the programmable IC with the respective ring oscillator circuits and determining respective delay values of the selected circuit elements from respective maximum frequencies of the ring oscillator circuits; and storing the delay values in association with identifiers of the selected circuit elements in a memory arrangement.
地址 San Jose CA US