Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit

摘要

To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.

主权项

1. A method for controlling first, second, third, fourth, fifth and sixth unit output buffers each having a first plurality of transistors connected between a power supply terminal and a data terminal comprising:
receiving a first plurality of impedance control signals; receiving first, second, and third selection signals; turning-on ones of the first plurality of transistors in the first unit buffer if corresponding ones of the first plurality of impedance control signals are activated and the first selection signal is activated; turning-off ones of the first plurality of transistors in the first unit buffer if corresponding ones of the first plurality of impedance control signals are deactivated or the first selection signal is deactivated; turning-on ones of the first plurality of transistors in the second and third unit buffers if corresponding ones of the first plurality of impedance control signals are activated and the second selection signal is activated; turning-off ones of the first plurality of transistors in the second and third unit buffers if corresponding ones of the first plurality of impedance control signals are deactivated or the second selection signal is deactivated; turning-on ones of the first plurality of transistors in the fourth, fifth and sixth unit buffers if corresponding ones of the first plurality of impedance control signals are activated and the third selection signal is activated; and turning-off ones of the first plurality of transistors in the fourth, fifth and sixth unit buffers if corresponding ones of the first plurality of impedance control signals are deactivated or the third selection signal is deactivated.