PHASE ERROR DETECTION IN PHASE LOCK LOOP AND DELAY LOCK LOOP DEVICES

摘要

A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.

主权项

1. A lock detect circuit, comprising:
a first margin setter connected to a first comparator and a second comparator; a second margin setter connected to the first comparator and the second comparator; an OR gate connected to the first comparator and the second comparator; and a lock signal generation unit connected to the OR gate.