Instruction set architecture with extended register addressing using one or more primary opcode bits

摘要

A method and circuit arrangement selectively repurpose bits from a primary opcode portion of an instruction for use in decoding one or more operands for the instruction. Decode logic of a processor, for example, may be placed in a predetermined mode that decodes a primary opcode for an instruction that is different from that specified in the primary opcode portion of the instruction, and then utilize one or more bits in the primary opcode portion to decode one or more operands for the instruction. By doing so, additional space is freed up in the instruction to support a larger register file and/or additional instruction types, e.g., as specified by a secondary or extended opcode.

主权项

1. A method of executing instructions in a processor of a type including an auxiliary execution unit, the method comprising:
receiving first and second instructions from an instruction stream, wherein the first and second instructions are members of an instruction set architecture defined for the processor, and wherein each instruction in the instruction set architecture includes a primary opcode portion and an operand portion; in response to receiving the first and second instructions:
decoding the first and second instructions by determining primary opcodes for each of the first and second instructions from the respective primary opcode portions thereof and determining at least one operand for each of the first and second instructions from the respective operand portions thereof;storing a primary opcode in a primary opcode register in response to decoding the first instruction; andstoring a count in a count register in response to decoding the second instruction; and after receiving the first and second instructions, receiving a plurality of auxiliary instructions from the instruction stream, wherein a number of auxiliary instructions in the plurality of auxiliary instructions is equal to the count stored in the count register by the second instruction, wherein each of the plurality of auxiliary instructions includes a primary opcode portion that includes at least one bit used to decode an operand of such auxiliary instruction; and for each auxiliary instruction among the plurality of auxiliary instructions:
determining that the count stored in the count register is a non-zero value;decoding a primary opcode for such auxiliary instruction based upon the primary opcode stored in the primary opcode register;decoding a secondary opcode for such auxiliary instruction from a secondary opcode portion of such auxiliary instruction, wherein the secondary opcode portion is different from the primary opcode portion;decoding a plurality of operands for such auxiliary instruction, wherein decoding the plurality of operands for such auxiliary instruction includes decoding first and second operands for such auxiliary instruction, wherein decoding the first operand includes concatenating at least one most significant bit for the first operand that is encoded in the primary opcode portion of such auxiliary instruction with a first plurality of least significant bits for the first operand encoded in an operand portion of such auxiliary instruction, and wherein decoding the second operand includes concatenating at least one most significant bit for the second operand that is encoded in the primary opcode portion of such auxiliary instruction with a second plurality of least significant bits for the second operand encoded in an operand portion of such auxiliary instruction, wherein a number of bits in the at least one most significant bit for the first operand is equal to a number of bits in the at least one most significant bit for the second operand;executing such auxiliary instruction in the auxiliary execution unit using the primary opcode, secondary opcode and plurality of operands decoded from such auxiliary instruction; anddecrementing the count stored in the count register.