SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME

摘要

A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit performs an error correction code (ECC) encoding on write data to be stored in the memory cell array, and performs an ECC decoding on read data from the memory cell array. The control logic circuit controls access to the memory cell array and generates an engine configuration selection signal based on a command. The error correction circuit reconfigures a number of units for which ECC including the ECC encoding and the ECC decoding is performed, in response to the engine configuration selection signal.

主权项

1. A semiconductor memory device, comprising:
a memory cell array; an error correction circuit configured to perform an error correction code (ECC) encoding on write data to be stored in the memory cell array, and configured to perform an ECC decoding on read data from the memory cell array; and a control logic circuit configured to control access to the memory cell array and configured to generate an engine configuration selection signal based on a command, wherein the error correction circuit is configured to reconfigure a number of units for which ECC including the ECC encoding and the ECC decoding is performed, in response to the engine configuration selection signal, and wherein each unit for which ECC is performed corresponds to correcting an error bit among the read data having n bits, wherein n is a natural number greater than 2 and is variable in response to the engine configuration selection signal.