| 发明名称 | Resistive switching memory | ||
| 摘要 | In one embodiment of the present invention, a memory cell includes a first resistive switching element having a first terminal and a second terminal, and a second resistive switching element having a first terminal and a second terminal. The memory further includes a three terminal transistor, which has a first terminal, a second terminal, and a third terminal. The first terminal of the three terminal transistor is coupled to the first terminal of the first resistive switching element. The second terminal of the three terminal transistor is coupled to the first terminal of the second resistive switching element. The third terminal of the three terminal transistor is coupled to a word line. | ||
| 申请公布号 | US9627441(B2) | 申请公布日期 | 2017.04.18 |
| 申请号 | US201414552250 | 申请日期 | 2014.11.24 |
| 申请人 | ADESTO TECHNOLOGIES CORPORATION | 发明人 | Van Buskirk Michael A. |
| 分类号 | H01L29/06;H01L27/24;G11C13/00;H01L27/06;H01L29/78;H01L29/861 | 主分类号 | H01L29/06 |
| 代理机构 | Slater Matsil, LLP | 代理人 | Slater Matsil, LLP |
| 主权项 | 1. A memory cell comprising: a first resistive switching element comprising a first high resistance state and a first low resistance state and having a first terminal and a second terminal; a second resistive switching element comprising a first high resistance state and a first low resistance state and having a first terminal and a second terminal; a field effect transistor having a first source/drain and a second source/drain, the first source/drain coupled to the first terminal of the first resistive switching element, the second source/drain coupled to the first terminal of the second resistive switching element; a first diode having a first terminal and a second terminal; and a second diode having a first terminal and a second terminal, wherein the first source/drain is coupled to the first terminal of the first diode, and wherein the second source/drain is coupled to the first terminal of the second diode. | ||
| 地址 | Sunnyvale CA US | ||