发明名称 Method and Structure of Three-Dimensional Chip Stacking
摘要 A method includes placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer. The first composite wafer is bonded to a second wafer, and the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding. The method further includes de-bonding the first carrier from the first plurality of device dies, encapsulating the first plurality of device dies in an encapsulating material, and forming an interconnect structure over the first plurality of device dies and the encapsulating material.
申请公布号 US2017103973(A1) 申请公布日期 2017.04.13
申请号 US201514951813 申请日期 2015.11.25
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Yu Chen-Hua;Chiou Wen-Chih;Lin Yung-Chi
分类号 H01L25/00;H01L23/498;H01L21/48;H01L23/31;H01L25/065;H01L21/56 主分类号 H01L25/00
代理机构 代理人
主权项 1. A method comprising: placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer; bonding the first composite wafer to a second wafer, wherein the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding, wherein after the bonding, the first plurality of device dies is located between the first carrier and the second wafer; de-bonding the first carrier from the first plurality of device dies; encapsulating the first plurality of device dies in an encapsulating material; and forming an interconnect structure over the first plurality of device dies and the encapsulating material.
地址 Hsin-Chu TW