Array substrate and manufacturing method thereof, display device

摘要

An array substrate and a manufacturing method thereof as well as a display device are disclosed. The array substrate includes a gate (21) and a gate insulating layers (22) of TFT formed in this order on a surface of a base substrate (20); a semiconductor active layer (23), an etching stop layer (24), and a source (251)/drain (252) of the TFT formed in this order on a surface of the gate insulating layer (22) corresponding to the gate (21) of the TFT. The source (251) and drain (252) of the TFT contact the semiconductor active layer (23) through respective vias. The array substrate further includes: a shielding electrode (26) formed between the gate (21) of the TFT and the base substrate (20); and an insulating layer (27) formed between the gate (21) of the TFT and the shielding electrode (26). In a region where the gate (21) faces the source (251), the area of the gate (210) is smaller than that of the source (251); and/or in a region where the gate (21) faces the drain (252), the area of the gate (210) is smaller than that of the drain (252). The array substrate according to embodiments of the present invention reduces the parasitic capacitance between the source/drain and the gate of the TFT and improves the quality of a display device.

主权项

1. An array substrate, comprising:
a gate of a TFT and a gate insulating layer formed on a surface of a base substrate, and the gate being formed between the substrate and the gate insulating layer; a semiconductor active layer, an etching stop layer, a source and a drain of the TFT sequentially formed on a surface of the gate insulating layer that corresponds to the gate of the TFT, the source and the drain contacting the semiconductor active layer through vias respectively; the array substrate further comprising: a shielding electrode formed between the gate of the TFT and the base substrate; and an insulating layer formed between the gate of the TFT and the shielding electrode; wherein an overlapping area of vertical projections of the gate and the source on the array substrate is smaller than an overlapping area of vertical projections of the shielding electrode and the source on the array substrate; and/or an overlapping area of vertical projections of the gate and the drain on the array substrate is smaller than an overlapping area of vertical projections of the shielding electrode and the drain on the array substrate, and wherein the shielding electrode is made of conductive material and a capacitance is generated between the gate and the shielding electrode and a length of the shielding electrode in a direction in which the source is opposite to the drain is shorter than a length of the gate in the direction in which the source is opposite to the drain.