Class-B/C Doherty power amplifier

摘要

It is provided an amplifier arrangement for optimizing efficiency at a peak power level and a back-off power level γ. The amplifier arrangement comprises an input power splitter dividing an input signal into a first signal having a power Pm and a second signal having a power Pa, a main transistor operating in a class-B like mode receiving the first signal, an auxiliary transistor operating in a class-C mode receiving the second signal. The received first and second signals have a phase offset value θ, wherein −π<θ<π. The amplifier arrangement further comprises a combining network. Circuit element values of the combining network, the power Pm and the power Pa, the phase offset value θ, a bias condition of the auxiliary transistor; and a relative size Saux of the auxiliary transistor, are based on a predetermined back-off power level γ, a current scaling factor rc of the auxiliary transistor, a main transistor oversizing factor ro,m, and an auxiliary transistor oversizing factor ro,a, where rc<1, ro,m≧1 and ro,a≧1. It is also provided a method for determining properties for an amplifier arrangement.

主权项

1. An amplifier arrangement for optimizing efficiency at a peak power level and a back-off power level γ, the amplifier arrangement comprising:
an input power splitter configured to divide an input signal into a first signal having a power Pm and a second signal having a power Pa; a main transistor connected to the power splitter and arranged to receive the first signal, the main transistor being configured to operate in a class-B like mode of operation to provide a first output signal; an auxiliary transistor connected to the power splitter and arranged to receive the second signal, the auxiliary transistor being configured to operate in a class-C mode of operation to provide a second output signal, wherein the received first and second signals have a phase offset value θ, wherein −π<θ<π; and; and a combining network configured to couple the first and second output signals of the main and auxiliary transistors to an output node of the amplifier arrangement, wherein circuit element values of the combining network, the power Pm and the power Pa; the phase offset value θ, a bias condition of the auxiliary transistor; and a relative size Saux of the auxiliary transistor are based on a predetermined back-off power level γ, a current scaling factor rc of the auxiliary transistor, a main transistor oversizing factor ro,m, and an auxiliary transistor oversizing factor ro,a, where rc<1, ro,m≧1 and ro,a≧1.