| 摘要 |
There is provided a shift register unit and driving method for the shift register unit, a shift register and a display device. The shift register unit comprises a first capacitor (C1), an input buffering module (31), a pulling-up module (32), a reset control module (33), a pulling-down module (34) and a pulling-down enhancement module (35); the pulling-down module (34) is configured to reduce the level at the signal output terminal (OUTPUT) and discharge the first capacitor (C1) during a first noise-removal phase; the pulling-down enhancement module (35) is configured to control, in cooperation with the pulling-down module (34), to continuously reduce the level at the signal output terminal (OUTPUT) and continuously discharge the first capacitor (C1) during a second noise-removal phase. Noise in the output signals of the shift register can be reduced and reliability of the shift register can be improved. |
| 主权项 |
1. A stage of shift register unit in a shift register, the stage of shift register unit comprises a first capacitor, an input buffering module, a pulling-up module, a reset control module, a pulling-down module and a pulling-down enhancement module, wherein
the input buffering module is directly connected to a start signal input terminal, the pulling-down module, a first terminal of the first capacitor and the pulling-up module, and is configured to pre-charge the first capacitor during a signal input buffering phase; the pulling-up module is directly connected to a first clock signal input terminal, the first capacitor, the input buffering module, the pulling-down module and a signal output terminal, and is configured to control the signal output terminal to output a driving signal during a signal output phase; the reset control module is directly connected to a reset signal input terminal, a low level signal input terminal and the pulling-down module, and is configured to control the pulling-down module to be in an OFF state during a reset phase; the pulling-down module is directly connected to a second clock signal input terminal, the low level signal input terminal, the signal output terminal, the input buffering module, the first capacitor, the pulling-up module and the reset control module, and is configured to reduce the level at the signal output terminal and discharge the first capacitor during a first noise-removal phase; and the pulling-down enhancement module is directly connected to the first clock signal input terminal and the pulling-down module, and is configured, in cooperation with the pulling-down module, to continuously reduce the level at the signal output terminal and continuously discharge the first capacitor during a second noise-removal phase; wherein the pulling-up module comprises a third transistor having a gate directly connected to a first node, a first electrode directly connected to the first clock signal input terminal and a second electrode directly connected to the signal output terminal; the signal output terminal is configured to directly provide a trigger signal to the start signal input terminal of a next stage of shift register unit. |
