发明名称 |
OSCILLATION CIRCUIT |
摘要 |
Provided is an oscillation circuit that can limit a maximum value and a minimum value of a frequency even when some troubles are caused in a V/I conversion circuit. The oscillation circuit includes a current controlled oscillator configured to oscillate based on an input current, and a current limiting circuit configured to: compare the input current with a first constant current and with a second constant current; limit, when the input current reaches the first constant current, a maximum current value of the input current with a transistor arranged on a path of the input current; and limit, when the input current is lowered to the second constant current, a minimum current of the input current through addition of current on the path of the input current by a transistor arranged in parallel with the path of the input current. |
申请公布号 |
US2017093334(A1) |
申请公布日期 |
2017.03.30 |
申请号 |
US201615272695 |
申请日期 |
2016.09.22 |
申请人 |
SII Semiconductor Corporation |
发明人 |
TAKADA Kosuke |
分类号 |
H03B5/12;H02M3/07 |
主分类号 |
H03B5/12 |
代理机构 |
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代理人 |
|
主权项 |
1. An oscillation circuit, comprising:
a current source circuit configured to generate a second current based on a first current flowing through a first current path between a power supply terminal and a current input terminal; and a current controlled oscillator configured to oscillate based on the second current, the current source circuit comprising:
a first PMOS transistor arranged on the first current path, and including a gate and a drain connected to each other;a second PMOS transistor forming a current mirror circuit with the first PMOS transistor, the second PMOS transistor being configured to cause the second current to flow therethrough;a third PMOS transistor forming a current mirror circuit with the first PMOS transistor;a constant current source connected to a drain of the third PMOS transistor; anda fourth PMOS transistor configured to limit a current value of the first current, and including a gate being controlled by a voltage of the drain of the third PMOS transistor. |
地址 |
Chiba-shi JP |