发明名称 |
LOW-OVERHEAD HARDWARE PREDICTOR TO REDUCE PERFORMANCE INVERSION FOR CORE-TO-CORE DATA TRANSFER OPTIMIZATION INSTRUCTIONS |
摘要 |
Apparatus and methods implementing a hardware predictor for reducing performance inversions caused by intra-core data transfer during inter-core data transfer optimization for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache or mid-level cache (MLC) for each core and a shared L3 or lastlevel cache (LLC). A hardware predictor to monitor accesses to sample cache lines and, based on these accesses, adaptively control the enablement of cache line demotion instructions for proactively demoting cache lines from lower cache levels to higher cache levels, including demoting cache lines from L1 or L2 caches (MLC) to L3 cache (LLC). |
申请公布号 |
WO2017053858(A1) |
申请公布日期 |
2017.03.30 |
申请号 |
WO2016US53528 |
申请日期 |
2016.09.23 |
申请人 |
INTEL CORPORATION |
发明人 |
WANG, Ren;HERDRICH, Andrew J.;WILKERSON, Christopher B. |
分类号 |
G06F12/0811 |
主分类号 |
G06F12/0811 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|