STORED DATA WITH TEMPORAL PROXIMITY ANALYSIS FOR VERY LARGE SCALE DATA WITH VERY LOW BUILT IN LATENCY

摘要

A system comprises a hashing logic, which executes instructions to convert raw data into a first logical address and payload data, where the first logical address describes metadata about the payload data. A hardware translation unit executes instructions to translate the first logical address into a first physical address on a storage device. A hardware load/storage unit stores the first logical address and the payload data at the first physical address on the storage device. A content addressable store is associated with a reference to the logical addressed data in this location addressable high dimensional store, where the content addressable store is searched for the desired content word using at least one temporal attribute to retrieve the corresponding references with low latency. A hardware exclusive OR (XOR) unit compares two logical address vectors to derive a Hamming distance between the two logical address vectors.

主权项

1. A memory system, comprising:
a location addressable high-dimensional store having data identified by location; a plurality of content addressable stores each having content words, each content word being associated with a reference to data in the location addressable high-dimensional store; a mapping unit that maps the location addressable high-dimensional store to a sparse distributed memory space; search word register for searching a content addressable store level for a desired content word using at least one temporal attribute; sparse memory retrieval unit that uses the desired content word to retrieve data from the sparse distributed memory space via the location addressable high-dimensional store which has been mapped; comparison unit to execute instructions to analyze the data which has been retrieved from the sparse distributed memory space by
a hashing logic, wherein the hashing logic executes instructions to convert the data which has been retrieved from the sparse distributed memory space into a first logical address and payload data, wherein the first logical address describes metadata about the payload data;a hardware translation unit, wherein the hardware translation unit executes instructions to translate the first logical address into a first physical address on a storage device;a hardware load/storage unit, wherein the hardware load/storage unit stores the first logical address and the payload data at the first physical address on the storage device;a hardware exclusive OR (XOR) unit, wherein the hardware XOR unit compares two logical address vectors to derive a Hamming distance between the two logical address vectors; anda hardware retrieval unit, wherein the hardware retrieval unit retrieves other payload data that is stored at a second physical address whose second logical address is within a predefined Hamming distance from the first logical address, and wherein a Hamming distance between the first logical address and the second logical address is derived by the hardware XOR unit.