发明名称 |
Integrated circuit product with bulk and SOI semiconductor devices |
摘要 |
An integrated circuit product is disclosed including an SOI structure including a bulk semiconductor substrate, a buried insulation layer positioned on the bulk semiconductor substrate and a semiconductor layer positioned on the insulation layer, wherein, in a first region of the SOI structure, the semiconductor layer and the buried insulation layer are removed and, in a second region of the SOI structure, the semiconductor layer and the buried insulation layer are present above the bulk semiconductor substrate. The product further includes a semiconductor bulk device comprising a first gate structure positioned on the bulk semiconductor substrate in the first region and an SOI semiconductor device comprising a second gate structure positioned on the semiconductor layer in the second region, wherein the first and second gate structures have a final gate height substantially extending to a common height level above an upper surface of the bulk semiconductor substrate. |
申请公布号 |
US9608003(B2) |
申请公布日期 |
2017.03.28 |
申请号 |
US201615193770 |
申请日期 |
2016.06.27 |
申请人 |
GLOBALFOUNDRIES Inc. |
发明人 |
Baars Peter;Moll Hans-Peter;Hoentschel Jan |
分类号 |
H01L29/49;H01L27/12;H01L21/308;H01L21/321;H01L21/762;H01L21/84;H01L27/06;H01L49/02;H01L29/08;H01L29/417;H01L29/66;H01L29/78 |
主分类号 |
H01L29/49 |
代理机构 |
Amerson Law Firm, PLLC |
代理人 |
Amerson Law Firm, PLLC |
主权项 |
1. An integrated circuit product, comprising:
an SOI structure comprising:
a bulk semiconductor substrate;a buried insulation layer positioned on said bulk semiconductor substrate; anda semiconductor layer positioned on said buried insulation layer, wherein, in a first region of said SOI structure, said semiconductor layer and said buried insulation layer are removed and, in a second region of said SOI structure, said semiconductor layer and said buried insulation layer are present above said bulk semiconductor substrate; a semiconductor bulk device comprising a first gate structure positioned on said bulk semiconductor substrate in said first region; and an SOI semiconductor device comprising a second gate structure positioned on said semiconductor layer in said second region, wherein said first and second gate structures have a final gate height substantially extending to a common height level above an upper surface of said bulk semiconductor substrate. |
地址 |
Grand Cayman KY |