发明名称 Method and apparatus for sharing instruction scheduling resources among a plurality of execution threads in a multi-threaded processor architecture
摘要 A microprocessor includes a front end module and a schedule queue module. The front end module is configured to retrieve first instructions, corresponding to a first thread, from an instruction cache, and retrieve second instructions, corresponding to a second thread, from the instruction cache. The front end module is also configured to decode the first instructions into first decoded instructions, and decode the second instructions into second decoded instructions. The schedule queue module is configured to selectively store the first decoded instructions and the second decoded instructions from the front end module and, for each stored decoded instruction, selectively issue the stored decoded instruction to an execution module. The schedule queue is further configured to reject storing an additional one of the first decoded instructions from the front end module in response to a count of the stored first decoded instructions in the schedule queue module exceeding a threshold.
申请公布号 US9606800(B1) 申请公布日期 2017.03.28
申请号 US201313836145 申请日期 2013.03.15
申请人 Marvell International Ltd. 发明人 Hameenanttila Tom;O'Bleness R. Frank;Jamil Sujat;Delgross Joseph
分类号 G06F9/30;G06F11/07;G06F9/38;G06F9/50;G06F9/48 主分类号 G06F9/30
代理机构 代理人
主权项 1. A microprocessor comprising: a front end module configured to retrieve first instructions, corresponding to a first thread, from an instruction cache,retrieve second instructions, corresponding to a second thread, from the instruction cache,decode the first instructions into first decoded instructions, anddecode the second instructions into second decoded instructions; and a schedule queue module configured to selectively store the first decoded instructions and the second decoded instructions from the front end module for future issuance, andfor each stored decoded instruction, selectively issue the stored decoded instruction to an execution module, wherein the schedule queue module is configured to reject storing an additional one of the first decoded instructions from the front end module in response to a count of the stored first decoded instructions in the schedule queue module exceeding a first threshold, wherein the first threshold is smaller than a total number of instructions that the schedule queue module is capable of storing, and wherein the first threshold is based on a difference between (i) the total number of instructions and (ii) a total number of threads serviced by the front end module.
地址 Hamilton BM