GENERATION AND USE OF MEMORY ACCESS INSTRUCTION ORDER ENCODINGS

摘要

Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes selecting a next memory load or memory store instruction to execute based on dependencies encoded within the block, and on a store vector that stores data indicating which memory load and memory store instructions in the instruction block have executed. The store vector can be masked using a store mask. The store mask can be generated when decoding the instruction block, or copied from an instruction block header. Based on the encoded dependencies and the masked store vector, the next instruction can issue when its dependencies are available.

主权项

1. An apparatus comprising memory and one or more block-based processor cores, at least one of the cores comprising:
an execution unit configured to execute memory access instructions comprising a plurality of memory load and/or memory store instructions contained in an instruction block; a hardware structure storing data indicating execution ordering of at least some of the memory access instructions; and a control unit configured to control issuing of the memory access instructions to the execution unit based at least in a part on the hardware structure data.