发明名称 UTILIZING PIPELINE REGISTERS AS INTERMEDIATE STORAGE
摘要 In one example, a method includes responsive to receiving, by a processing unit, one or more instructions requesting that a first value be moved from a first general purpose register (GPR) to a third GPR and that a second value be moved from a second GPR to a fourth GPR, copying, by an initial logic unit and during a first clock cycle, the first value to an initial pipeline register, copying, by the initial logic and during a second clock cycle, the second value to the initial pipeline register, copying, by a final logic unit and during a third clock cycle, the first value from a final pipeline register to the third GPR, and copying, by the final logic unit and during a fourth clock cycle, the second value from the final pipeline register to the fourth GPR.
申请公布号 EP3143495(A1) 申请公布日期 2017.03.22
申请号 EP20150724805 申请日期 2015.04.21
申请人 Qualcomm Incorporated 发明人 CHEN, Lin;DU, Yun;UDAYAKUMARAN, Sumesh;ZHANG, Chihong;GRUBER, Andrew Evan
分类号 G06F9/30;G06F9/38 主分类号 G06F9/30
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