Semiconductor device with six transistors forming a NAND circuit

摘要

A semiconductor device has a small area and constitutes a CMOS 3-input NAND circuit by using surrounding gate transistors (SGTs) that are vertical transistors. In a 3-input NAND circuit including six MOS transistors arranged in a line, the MOS transistors constituting the NAND circuit have the following configuration. Planar silicon layers are disposed on a substrate. The drain, gate, and source of the MOS transistors are arranged in a vertical direction, and the gate surrounds a silicon pillar. The planer silicon layers include a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicide layer disposed on surfaces of the planar silicon layers. In this way, a semiconductor device constituting a NAND circuit with a small area is provided.

主权项

1. A semiconductor device, comprising:
six transistors arranged in a line on a substrate to constitute a NAND circuit, each of said six transistors having a source, a drain, and a gate arranged hierarchically in a direction perpendicular to said substrate, and each of said six transistors having: a silicon pillar; an insulator surrounding a side surface of said silicon pillar; a gate surrounding said insulator; a source region disposed at an upper portion or lower portion of said silicon pillar; and a drain region disposed at an upper portion or lower portion of said silicon pillar on a side of said silicon pillar opposite said source region; said six transistors including:
a first p-channel MOS transistor,a second p-channel MOS transistor,a third p-channel MOS transistor,a first n-channel MOS transistor,a second n-channel MOS transistor, anda third n-channel MOS transistor; wherein: the gate of said first p-channel MOS transistor and the gate of said first n-channel MOS transistor are connected to each other; the gate of said second p-channel MOS transistor and the gate of said second n-channel MOS transistor are connected to each other, the gate of said third p-channel MOS transistor and the gate of said third n-channel MOS transistor are connected to each other, the drain region of said first p-channel MOS transistor, the drain region of said second p-channel MOS transistor, the drain region of said third p-channel MOS transistor, the drain region of said first n-channel MOS transistor, and the drain region of said third n-channel MOS transistor are disposed on a side of the silicon pillars close to the substrate, the source region of said second n-channel MOS transistor is disposed on a side of the silicon pillar close to the substrate, the drain region of said first p-channel MOS transistor, the drain region of said second p-channel MOS transistor, the drain region of said third p-channel MOS transistor, and the drain region of said first n-channel MOS transistor are connected to one another via a silicide region, the source region of said first n-channel MOS transistor and the drain region of said second n-channel MOS transistor are connected to each other via a contact, and the source region of said second n-channel MOS transistor and the drain region of said third n-channel MOS transistor are connected to each other via the silicide region.