| 发明名称 |
PARTIALLY BIASED ISOLATION IN SEMICONDUCTOR DEVICES |
| 摘要 |
A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region. |
| 申请公布号 |
US2017077295(A1) |
申请公布日期 |
2017.03.16 |
| 申请号 |
US201514851360 |
申请日期 |
2015.09.11 |
| 申请人 |
Freescale Semiconductor, Inc. |
发明人 |
Yang Hongning;Blomberg Daniel J.;Cheng Xu;Lin Xin;Zhang Zhihong;Zuo Jiang-Kai |
| 分类号 |
H01L29/78;H01L29/06;H01L21/265;H01L29/10;H01L21/266;H01L29/66;H01L29/40 |
主分类号 |
H01L29/78 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A device comprising:
a semiconductor substrate; a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier; an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation; and a depleted well region disposed in the semiconductor substrate outside of the core device area, the depleted well region electrically coupling the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region. |
| 地址 |
Austin TX US |
